Design of zero bias power detectors towards power consumption optimization in 5G devices

This paper presents the design and characterization of zero bias power detectors, based on MOSFET transistors, integrated in SiGe 55-nm BiCMOS technology from ST-Microelectronics. The working frequency bands circuits are located range (38–55) GHz, dedicated to optimize consumption 5G devices. Three NMOS categories available used (GP, LP, HPA), aim is several detectors different order compare their performances. In addition, a detector stack 6 LP transistors designed increase dynamic range. Compared recent works, HPA exhibits very good performance with low noise equivalent value (NEP) 3.8 pW/Hz large 67 ​dB. extracted voltage sensitivity values these between (850–1400) V/W showing agreements simulation results.